LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 307
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
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Table 280: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014)
UM10360
User manual
Bit
0
1
2
3
4
5
6
Symbol
Receiver Data
Ready (RDR)
Overrun Error
(OE)
Parity Error (PE)
Framing Error
(FE)
Break Interrupt
(BI)
Transmitter
Holding Register
Empty (THRE))
Transmitter
Empty (TEMT)
bit description
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
UnLSR0 is set when the UnRBR holds an unread character and is cleared when
the UARTn RBR FIFO is empty.
The UARTn receiver FIFO is empty.
The UARTn receiver FIFO is not empty.
The overrun error condition is set as soon as it occurs. An UnLSR read clears
UnLSR1. UnLSR1 is set when UARTn RSR has a new character assembled and
the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be
overwritten and the character in the UARTn RSR will be lost.
Overrun error status is inactive.
Overrun error status is active.
When the parity bit of a received character is in the wrong state, a parity error
occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is
dependent on UnFCR[0].
Note: A parity error is associated with the character at the top of the UARTn RBR
FIFO.
Parity error status is inactive.
Parity error status is active.
When the stop bit of a received character is a logic 0, a framing error occurs. An
UnLSR read clears UnLSR[3]. The time of the framing error detection is
dependent on UnFCR0. Upon detection of a framing error, the Rx will attempt to
resynchronize to the data and assume that the bad stop bit is actually an early
start bit. However, it cannot be assumed that the next received byte will be correct
even if there is no Framing Error.
Note: A framing error is associated with the character at the top of the UARTn
RBR FIFO.
Framing error status is inactive.
Framing error status is active.
When RXDn is held in the spacing state (all zeroes) for one full character
transmission (start, data, parity, stop), a break interrupt occurs. Once the break
condition has been detected, the receiver goes idle until RXDn goes to marking
state (all ones). An UnLSR read clears this status bit. The time of break detection
is dependent on UnFCR[0].
Note: The break interrupt is associated with the character at the top of the UARTn
RBR FIFO.
Break interrupt status is inactive.
Break interrupt status is active.
THRE is set immediately upon detection of an empty UARTn THR and is cleared
on a UnTHR write.
UnTHR contains valid data.
UnTHR is empty.
TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when
either the UnTSR or the UnTHR contain valid data.
UnTHR and/or the UnTSR contains valid data.
UnTHR and the UnTSR are empty.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 14: LPC17xx UART0/2/3
UM10360
© NXP B.V. 2010. All rights reserved.
307 of 840
Reset
Value
0
0
0
0
0
1
1
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