LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 18

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
3.3 Register description
3.4 Reset
UM10360
User manual
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
Table 7.
Reset has 4 sources on the LPC17xx: the RESET pin, Watchdog Reset, Power On Reset
(POR), and Brown Out Detect (BOD).
The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once
the operating voltage attains a usable level, starts the wake-up timer (see description in
Section 4.9 “Wake-up timer”
external Reset is de-asserted, the oscillator is running, a fixed number of clocks have
passed, and the flash controller has completed its initialization. The reset logic is shown in
the following block diagram (see
Name
External Interrupts
EXTINT
EXTMODE
EXTPOLAR
Reset
RSID
Syscon Miscellaneous Registers
SCS
Summary of system control registers
Description
External Interrupt Flag Register
External Interrupt Mode register
External Interrupt Polarity Register
Reset Source Identification Register
System Control and Status
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
in this chapter), causing reset to remain asserted until the
Figure
4).
R/W
R/W
R/W
R/W
R/W
Access
Chapter 3: LPC17xx System control
Reset value
0
0
0
see
0
Table 8
UM10360
© NXP B.V. 2010. All rights reserved.
Address
0x400F C140
0x400F C148
0x400F C14C
0x400F C180
0x400F C1A0
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