LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 514

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
24.6 Register description
Table 445. PWM1 register map
UM10360
User manual
CR3
Generic
Name
IR
TCR
TC
PR
PC
MCR
MR0
MR1
MR2
MR3
CCR
CR0
CR1
CR2
Description
Interrupt Register. The IR can be written to clear interrupts. The IR can be
read to identify which of eight possible interrupt sources are pending.
Timer Control Register. The TCR is used to control the Timer Counter
functions. The Timer Counter can be disabled or reset through the TCR.
Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK.
The TC is controlled through the TCR.
Prescale Register. The TC is incremented every PR+1 cycles of PCLK.
Prescale Counter. The 32-bit PC is a counter which is incremented to the
value stored in PR. When the value in PR is reached, the TC is
incremented. The PC is observable and controllable through the bus
interface.
Match Control Register. The MCR is used to control if an interrupt is
generated and if the TC is reset when a Match occurs.
Match Register 0. MR0 can be enabled in the MCR to reset the TC, stop
both the TC and PC, and/or generate an interrupt when it matches the TC.
In addition, a match between this value and the TC sets any PWM output
that is in single-edge mode, and sets PWM1 if it’s in double-edge mode.
Match Register 1. MR1 can be enabled in the MCR to reset the TC, stop
both the TC and PC, and/or generate an interrupt when it matches the TC.
In addition, a match between this value and the TC clears PWM1 in either
edge mode, and sets PWM2 if it’s in double-edge mode.
Match Register 2. MR2 can be enabled in the MCR to reset the TC, stop
both the TC and PC, and/or generate an interrupt when it matches the TC.
In addition, a match between this value and the TC clears PWM2 in either
edge mode, and sets PWM3 if it’s in double-edge mode.
Match Register 3. MR3 can be enabled in the MCR to reset the TC, stop
both the TC and PC, and/or generate an interrupt when it matches the TC.
In addition, a match between this value and the TC clears PWM3 in either
edge mode, and sets PWM4 if it’s in double-edge mode.
Capture Control Register. The CCR controls which edges of the capture
inputs are used to load the Capture Registers and whether or not an
interrupt is generated when a capture takes place.
Capture Register 0. CR0 is loaded with the value of the TC when there is
an event on the CAPn.0 input.
Capture Register 1. See CR0 description.
Capture Register 2. See CR0 description.
Capture Register 3. See CR0 description.
The PWM1 function includes registers as shown in
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 24: LPC17xx Pulse Width Modulator (PWM)
Table 445
RO
RO
RO
Access Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
below.
0
0
0
Value
0
0
0
0
0
0
0
0
0
0
0
0
[1]
UM10360
© NXP B.V. 2010. All rights reserved.
PWMn Register
Name & Address
PWM1IR -
0x4001 8000
PWM1TCR -
0x4001 8004
PWM1TC -
0x4001 8008
PWM1PR -
0x4001 800C
PWM1PC -
0x4001 8010
PWM1MCR -
0x4001 8014
PWM1MR0 -
0x4001 8018
PWM1MR1 -
0x4001 801C
PWM1MR2 -
0x4001 8020
PWM1MR3 -
0x4001 8024
PWM1CCR -
0x4001 8028
PWM1CR0 -
0x4001 802C
PWM1CR1 -
0x4001 8030
PWM1CR2 -
0x4001 8034
PWM1CR3 -
0x4001 8038
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