LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 262

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
11.15.6.2 Finding the DMA Descriptor
11.15.6.3 Transferring the Data
11.15.6.4 DMA descriptor completion
11.15.6.5 Isochronous OUT Endpoint Operation Example
For isochronous endpoints, the DMA_buffer_length and Present_DMA_count fields are in
frames rather than bytes.
Finding the descriptors is done in the same way as that for a non-isochronous endpoint.
A DMA request will be placed for DMA-enabled isochronous endpoints on every FRAME
interrupt. On processing the request, the DMA engine will fetch the descriptor and if
Isochronous_endpoint is set, will fetch the Isochronous_packetsize_memory_address
from the fifth word of the DD.
The data is transferred to or from the memory location DMA_buffer_start_addr. After the
end of the packet transfer the Present_DMA_count value is incremented by 1.
The isochronous packet size is stored in memory as shown in
packet size memory shown is divided into fields: Frame_number (bits 31 to 17),
Packet_valid (bit 16), and Packet_length (bits 15 to 0). The space allocated for the packet
size memory for a given DD should be DMA_buffer_length words in size – one word for
each packet to transfer.
OUT endpoints
At the completion of each frame, the packet size is written to the address location in
Isochronous_packet_size_memory_address, and
Isochronous_packet_size_memory_address is incremented by 4.
IN endpoints
Only the Packet_length field of the isochronous packet size word is used. For each frame,
an isochronous data packet of size specified by this field is transferred from the USB
device to the host, and Isochronous_packet_size_memory_address is incremented by 4
at the end of the packet transfer. If Packet_length is zero, an empty packet will be sent by
the USB device.
DDs for isochronous endpoints can only end with a status code of NormalCompletion
since there is no short packet on Isochronous endpoints, and the USB transfer continues
indefinitely until a SystemError occurs. There is no DataOverrun detection for isochronous
endpoints.
Assume that an isochronous endpoint is programmed for the transfer of 10 frames and
that the transfer begins when the frame number is 21. After transferring four frames with
packet sizes of 10,15, 8 and 20 bytes without errors, the descriptor and memory map
appear as shown in
The_total_number_of_bytes_transferred = 0x0A + 0x0F + 0x08 + 0x14 = 0x35.
The Packet_valid bit (bit 16) of all the words in the packet length memory is set to 1.
All information provided in this document is subject to legal disclaimers.
Figure
Rev. 2 — 19 August 2010
31.
Chapter 11: LPC17xx USB device controller
Figure
31. Each word in the
UM10360
© NXP B.V. 2010. All rights reserved.
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