LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 783

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.4.4.1 SysTick Control and Status Register
34.4.4 System timer, SysTick
The processor has a 24-bit system timer, SysTick, that counts down from the reload value
to zero, reloads (wraps to) the value in the LOAD register on the next clock edge, then
counts down on subsequent clocks.
Note: refer to the separate chapter in the LPC17xx User Manual
device specific information on the System Timer.
Remark: when the processor is halted for debugging the counter does not decrement.
The system timer registers are:
Table 674. System timer registers summary
[1]
The SysTick CTRL register enables the SysTick features. See the register summary in
Table 674
Table 675. SysTick CTRL register bit assignments
When ENABLE is set to 1, the counter loads the RELOAD value from the LOAD register
and then counts down. On reaching 0, it sets the COUNTFLAG to 1 and optionally asserts
the SysTick depending on the value of TICKINT. It then loads the RELOAD value again,
and begins counting.
Address
0xE000E010
0xE000E014
0xE000E018
0xE000E01C
Bits
[31:17]
[16]
[15:3]
[2]
[1]
[0]
SysTick calibration value. This value is specific to LPC17xx devices.
Name
-
COUNTFLAG
-
CLKSOURCE
TICKINT
ENABLE
for its attributes. The bit assignments are shown in
Name
CTRL
LOAD
VAL
CALIB
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Type
RW
RW
RW
RO
Function
Reserved.
Returns 1 if timer counted to 0 since last time this was read.
Reserved.
Indicates the clock source:
0 = external clock
1 = processor clock.
Enables SysTick exception request:
0 = counting down to zero does not assert the SysTick exception
request
1 = counting down to zero to asserts the SysTick exception request.
Software can use COUNTFLAG to determine if SysTick has ever
counted to zero.
Enables the counter:
0 = counter disabled
1 = counter enabled.
Required
privilege
Privileged
Privileged
Privileged
Privileged
Chapter 34: Appendix: Cortex-M3 user guide
Reset
value
0x00000004
0x00000000
0x00000000
0x000F423F
[1]
Description
Table 675
Table 676
Table 677
Table 678
Table
675.
Section 23.1
UM10360
© NXP B.V. 2010. All rights reserved.
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