LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 230

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 210. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0x5000 C240) bit description
UM10360
User manual
Bit
31:0
Symbol
See USBEpIntPri bit
allocation table above
11.10.4.1 EP RAM requirements
11.10.4.2 USB Realize Endpoint register (USBReEp - 0x5000 C244)
11.10.4 Endpoint realization registers
The registers in this group allow realization and configuration of endpoints at run time.
The USB device controller uses a RAM based FIFO for each endpoint buffer. The RAM
dedicated for this purpose is called the Endpoint RAM (EP_RAM). Each endpoint has
space reserved in the EP_RAM. The EP_RAM space required for an endpoint depends
on its MaxPacketSize and whether it is double buffered. 32 words of EP_RAM are used by
the device for storing the endpoint buffer pointers. The EP_RAM is word aligned but the
MaxPacketSize is defined in bytes hence the RAM depth has to be adjusted to the next
word boundary. Also, each buffer has one word header showing the size of the packet
length received.
The EP_ RAM space (in words) required for the physical endpoint can be expressed as
where dbstatus = 1 for a single buffered endpoint and 2 for double a buffered endpoint.
Since all the realized endpoints occupy EP_RAM space, the total EP_RAM requirement is
where N is the number of realized endpoints. Total EP_RAM space should not exceed
4096 bytes (4 kB, 1 kwords).
Writing one to a bit in this register causes the corresponding endpoint to be realized.
Writing zeros causes it to be unrealized. This register returns to its reset state when a bus
reset occurs. USBReEp is a read/write register.
Value Description
0
1
The corresponding interrupt is routed to the EP_SLOW bit of
USBDevIntSt
The corresponding interrupt is routed to the EP_FAST bit of
USBDevIntSt
All information provided in this document is subject to legal disclaimers.
EPRAMspace
TotalEPRAMspace
Rev. 2 — 19 August 2010
=
⎛
⎝
------------------------------------------------- -
MaxPacketSize
=
Chapter 11: LPC17xx USB device controller
32
4
+
n
∑
N
=
0
EPRAMspace n ( )
+
3
+
1
⎞
⎠
×
dbstatus
UM10360
© NXP B.V. 2010. All rights reserved.
Reset value
0
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