LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 295

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
Fig 44. Clocking and power control
USB CLOCK
DIVIDER
PCUSB
cclk
13.10.1 Device clock request signals
usbclk
(48 MHz)
The Device controller has two clock request signals, dev_need_clk and
dev_dma_need_clk. When asserted, these signals turn on the device’s 48 MHz clock and
ahb_master_clk respectively.
The dev_need_clk signal is asserted while the device is not in the suspend state, or if the
device is in the suspend state and activity is detected on the USB bus. The dev_need_clk
signal is de-asserted if a disconnect is detected (CON bit is cleared in the SIE Get Device
Status register –
normal operation when software does not need to access the Device controller registers –
the Device will continue to function normally and automatically shut off its clock when it is
suspended or disconnected.
EN
EN
EN
EN
EN
SWITCH
SWITCH
SWITCH
SWITCH
SWITCH
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
ahb_master_clk
ahb_slave_clk
AHB_CLK_ON
DEV_CLK_ON
HOST_CLK_ON
OTG_CLK_ON
I2C_CLK_ON
All information provided in this document is subject to legal disclaimers.
Section
Rev. 2 — 19 August 2010
11.10.6). This signal allows DEV_CLK_EN to be cleared during
CONTROLLER
CONTROLLER
CONTROLLER
CONTROLLER
INTERFACE
REGISTER
DEVICE
HOST
HOST_CLK_EN
OTG
I2C
OTG_CLK_EN
DEV_CLK_EN
AHB_CLK_EN
I2C_CLK_EN
dev_dma_need_clk
dev_need_clk
host_dma_need_clk
host_need_clk
Chapter 13: LPC17xx USB OTG
ahb_need_clk
UM10360
© NXP B.V. 2010. All rights reserved.
USB_NEED_CLK
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