LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 422

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
18.6.2 SSPn Control Register 1 (SSP0CR1 - 0x4008 8004, SSP1CR1 -
Table 370: SSPn Control Register 0 (SSP0CR0 - address 0x4008 8000, SSP1CR0 -
0x4003 0004)
This register controls certain aspects of the operation of the SSP controller.
Bit
3:0
5:4
6
7
15:8
31:8
Symbol Value Description
DSS
FRF
CPOL
CPHA
SCR
-
0x4003 0000) bit description
All information provided in this document is subject to legal disclaimers.
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
00
01
10
11
0
1
0
1
Rev. 2 — 19 August 2010
Data Size Select. This field controls the number of bits
transferred in each frame. Values 0000-0010 are not supported
and should not be used.
4-bit transfer
5-bit transfer
6-bit transfer
7-bit transfer
8-bit transfer
9-bit transfer
10-bit transfer
11-bit transfer
12-bit transfer
13-bit transfer
14-bit transfer
15-bit transfer
16-bit transfer
Frame Format.
SPI
TI
Microwire
This combination is not supported and should not be used.
Clock Out Polarity. This bit is only used in SPI mode.
SSP controller maintains the bus clock low between frames.
SSP controller maintains the bus clock high between frames.
Clock Out Phase. This bit is only used in SPI mode.
SSP controller captures serial data on the first clock transition of
the frame, that is, the transition away from the inter-frame state
of the clock line.
SSP controller captures serial data on the second clock transition
of the frame, that is, the transition back to the inter-frame state of
the clock line.
Serial Clock Rate. The number of prescaler-output clocks per bit
on the bus, minus one. Given that CPSDVSR is the prescale
divider, and the APB clock PCLK clocks the prescaler, the bit
frequency is PCLK / (CPSDVSR × [SCR+1]).
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 18: LPC17xx SSP0/1
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
Value
0000
00
0
0
0x00
NA