LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 683

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.2.5.3.1 Syntax
34.2.5.3.2 Operation
34.2.5.3.3 Restrictions
34.2.5.3 ASR, LSL, LSR, ROR, and RRX
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate
Right with Extend.
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
where:
op is one of:
S is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see
Rd is the destination register.
Rm is the register holding the shift length to apply to the value in Rm. Only the least
significant byte is used and can be in the range 0 to 255.
Rs s the register holding the shift length to apply to the value in Rm. Only the least
significant byte is used and can be in the range 0 to 255.
n is the shift length. The range of shift length depends on the instruction:
Remark: MOV{S}{cond} Rd, Rm is the preferred syntax for LSL{S}{cond} Rd, Rm, #0.
ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of
places specified by constant n or register Rs.
RRX moves the bits in register Rm to the right by 1.
In all these instructions, the result is written to Rd, but the value in register Rm remains
unchanged. For details on what result is generated by the different instructions, see
Section 34.2.3.4 “Shift
Do not use SP and do not use PC.
ASR: Arithmetic Shift Right.
LSL: Logical Shift Left.
LSR: Logical Shift Right.
ROR: Rotate Right.
ASR: shift length from 1 to 32
LSL: shift length from 0 to 31
LSR: shift length from 1 to 32
ROR: shift length from 1 to 31
All information provided in this document is subject to legal disclaimers.
Section 34.2.3.7 “Conditional
Rev. 2 — 19 August 2010
Operations”.
Chapter 34: Appendix: Cortex-M3 user guide
execution”.
UM10360
© NXP B.V. 2010. All rights reserved.
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