LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 218

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
11.8 Pin description
11.9 Clocking and power management
UM10360
User manual
11.9.1 Power requirements
11.9.2 Clocks
Once data has been received or sent, the endpoint buffer can be read or written. How this
is accomplished depends on the endpoint’s type and operating mode. The two operating
modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode.
In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the
Register Interface. See
this mode.
In DMA mode, the DMA transfers data between RAM and the endpoint buffer. See
Section 11.15 “DMA operation”
Table 186. USB external interface
This section describes the clocking and power management features of the USB Device
Controller.
The USB protocol insists on power management by the device. This becomes very critical
if the device draws power from the bus (bus-powered device). The following constraints
should be met by a bus-powered device:
The USB device controller clocks are shown in
Name
V
USB_CONNECT
USB_UP_LED
USB_D+
USB_D-
1. A device in the non-configured state should draw a maximum of 100 mA from the bus.
2. A configured device can draw only up to what is specified in the Max Power field of
3. A suspended device can draw a maximum of 2.5 mA.
BUS
the configuration descriptor. The maximum value is 500 mA.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 11.14 “Slave mode operation”
Direction
I
O
O
I/O
I/O
for a detailed description of this mode.
Description
V
via its corresponding PINSEL register, it is driven
HIGH internally.
SoftConnect control signal.
GoodLink LED control signal.
Positive differential data.
Negative differential data.
BUS
Chapter 11: LPC17xx USB device controller
status input. When this function is not enabled
Table 187
for a detailed description of
UM10360
© NXP B.V. 2010. All rights reserved.
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