LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 764

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.4.2.8 Software Trigger Interrupt Register
34.4.2.9 Level-sensitive and pulse interrupts
Table 651. IPR bit assignments
See
provides the software view of the interrupt priorities.
Find the IPR number and byte offset for interrupt N as follows:
Write to the STIR to generate a Software Generated Interrupt (SGI). See the register
summary in
When the USERSETMPEND bit in the CCR is set to 1, unprivileged software can access
the STIR, see
Remark: Only privileged software can enable unprivileged access to the STIR.
The bit assignments are shown in
Table 652. STIR bit assignments
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also
described as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt
signal. Typically this happens because the ISR accesses the peripheral, causing it to clear
the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the
rising edge of the processor clock. To ensure the NVIC detects the interrupt, the
peripheral must assert the interrupt signal for at least one clock cycle, during which the
NVIC detects the pulse and latches the interrupt.
Bits
[31:24]
[23:16]
[15:8]
[7:0]
Bits
[31:9]
[8:0]
•
•
the corresponding IPR number, M, is given by M = N DIV 4
the byte offset of the required Priority field in this register is N MOD 4, where:
– byte offset 0 refers to register bits[7:0]
– byte offset 1 refers to register bits[15:8]
– byte offset 2 refers to register bits[23:16]
– byte offset 3 refers to register bits[31:24].
Table 645
Name
Priority, byte offset 3 Each priority field holds a priority value, 0-31. The lower the
Priority, byte offset 2
Priority, byte offset 1
Priority, byte offset 0
Table 644
Field
-
INTID
Section 34.4.3.8 “Configuration and Control
for more information about the IP[0] to IP[111] interrupt priority array, that
All information provided in this document is subject to legal disclaimers.
Function
of b000000011 specifies interrupt IRQ3.
Reserved.
Interrupt ID of the required SGI, in the range 0-111. For example, a value
Rev. 2 — 19 August 2010
for the STIR attributes.
Function
value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:3] of each field, bits[2:0]
read as zero and ignore writes.
Table
652.
Chapter 34: Appendix: Cortex-M3 user guide
Register”.
UM10360
© NXP B.V. 2010. All rights reserved.
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