LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 616

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
Fig 136. Map of lower memory
32.3.1.1 Criterion for Valid User Code
32.3.1 Memory map after any reset
A hardware flash signature generation capability is built into the flash memory. this feature
can be used to create a signature that can then be used to verify flash contents. Details of
flash signature generation are in
When a user program begins execution after reset, the interrupt vectors are set to point to
the beginning of flash memory.
The reserved Cortex-M3 exception vector location 7 (offset 0x 001C in the vector table)
should contain the 2’s complement of the check-sum of table entries 0 through 6. This
causes the checksum of the first 8 table entries to be 0. The boot loader code checksums
the first 8 locations in sector 0 of the flash. If the result is 0, then execution control is
transferred to the user code.
If the signature is not valid, the auto-baud routine synchronizes with the host via serial port
0. The host should send a “?” (0x3F) as a synchronization character and wait for a
response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity.
The auto-baud routine measures the bit time of the received synchronization character in
terms of its own frequency and programs the baud rate generator of the serial port. It also
All information provided in this document is subject to legal disclaimers.
Chapter 32: LPC17xx Flash memory interface and programming
Rev. 2 — 19 August 2010
Section
32.10.
UM10360
© NXP B.V. 2010. All rights reserved.
616 of 840