LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 281

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
13.8.10 I
13.8.9 OTG Clock Status Register (OTGClkSt - 0x5000 CFF8)
Table 261. OTG clock control register (OTG_clock_control - address 0x5000 CFF4) bit
This register holds the clock availability status. When enabling a clock via OTGClkCtrl,
software should poll the corresponding bit in this register. If it is set, then software can go
ahead with the register access. Software does not have to repeat this exercise for every
access, provided that the OTGClkCtrl bits are not disturbed.
Table 262. OTG clock status register (OTGClkSt - address 0x5000 CFF8) bit description
This register is the top byte of the receive FIFO. The receive FIFO is 4 bytes deep. The Rx
FIFO is flushed by a hard reset or by a soft reset (I2C_CTL bit 7). Reading an empty FIFO
gives unpredictable data results.
Bit
4
31:5
Bit
0
1
2
3
4
31:5
2
C Receive Register (I2C_RX - 0x5000 C300)
Symbol
AHB_CLK_EN
-
Symbol
HOST_CLK_ON
DEV_CLK_ON
I2C_CLK_ON
OTG_CLK_ON
AHB_CLK_ON
-
description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Value Description
0
1
NA
Value Description
0
1
0
1
0
1
0
1
0
1
NA
AHB master clock enable
Disable the AHB clock.
Enable the AHB clock.
Reserved, user software should not write ones
to reserved bits. The value read from a
reserved bit is not defined.
Host clock status.
Host clock is not available.
Host clock is available.
Device clock status.
Device clock is not available.
Device clock is available.
I
I
I
OTG clock status.
OTG clock is not available.
OTG clock is available.
AHB master clock status.
AHB clock is not available.
AHB clock is available.
Reserved, user software should not write ones
to reserved bits. The value read from a
reserved bit is not defined.
2
2
2
C clock status.
C clock is not available.
C clock is available.
Chapter 13: LPC17xx USB OTG
UM10360
© NXP B.V. 2010. All rights reserved.
281 of 840
Reset
Value
0
NA
Reset
Value
0
0
0
NA
0
0