LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 399

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
Fig 73. ID Look-up table configuration example (FullCAN activated and enabled)
SFF_GRP_sa =
EFF_GRP_sa =
ENDofTable =
SFF_sa
= 0x10
EFF_sa =
0x20
16.17.8 Look-up table programming guidelines
...
...
Message
Standard
Identifier
FullCAN
Section
Standard
Section
section
FullCAN
Identifier
Section
Explicit
Format
Frame
Object
Explicit
Format
Frame
All identifier sections of the ID Look-up Table have to be programmed in such a way, that
each active section is organized as a sorted list or table with an increasing order of the
Source CAN Channel (SCC) together with CAN Identifier in each section.
SCC value equals CAN_controller - 1, i.e., SCC = 0 matches CAN1 and SCC = 1
matches CAN2.
In cases, where a syntax error in the ID Look-up Table is encountered, the Look-up Table
address of the incorrect line is made available in the Look-up Table Error Address
Register (LUTerrAd).
The reporting process in the Look-up Table Error Address Register (LUTerrAd) is a
“run-time” process. Only those address lines with syntax error are reported, which were
passed through the acceptance filtering process.
The following general rules for programming the Look-up Table apply:
SCC
SCC
SCC
SCC
SCC
SCC
SCC
SCC
Disable bit
Message
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28
All information provided in this document is subject to legal disclaimers.
Enable bit
FullCAN
Interrupt
10
12
14
0
2
4
6
8
Rev. 2 — 19 August 2010
No Message Data, disabled.
No Message Data, disabled.
No Message Data, disabled.
FF RTR SEM DLC CAN-ID
FF RTR SEM DLC CAN-ID
Index
RXDATA 4, 3, 2, 1
RXDATA 8, 7, 6, 5
RXDATA 4, 3, 2, 1
RXDATA 8, 7, 6, 5
ID18
ID18
ID18
ID18
ID18
ID18
ID18
ID18
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
SCC
SCC
SCC
SCC
SCC
SCC
SCC
SCC
Disable bit
Message
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28
Enable bit
FullCAN
Interrupt
Disabled, 1
11
13
15
3
5
7
9
Chapter 16: LPC17xx CAN1/2
ID18
ID18
ID18
ID18
ID18
ID18
ID18
ID18
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
UM10360
Message Object
© NXP B.V. 2010. All rights reserved.
Message Object
Message Object
Data 0
Data 2
Data 1
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