LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 458

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 399. Master Receiver mode
UM10360
User manual
I2CSTAT
Status
Code
0x08
0x10
0x38
0x40
0x48
0x50
0x58
Status of the
I
hardware
A START condition
has been transmitted.
A repeated START
condition has been
transmitted.
Arbitration lost in
NOT ACK bit.
SLA+R has been
transmitted; ACK has
been received.
SLA+R has been
transmitted; NOT
ACK has been
received.
Data byte has been
received; ACK has
been returned.
Data byte has been
received; NOT ACK
has been returned.
2
C-bus and
Application software response
To/From I2DAT
Load SLA+R
Load SLA+R or
Load SLA+W
No I2DAT action or
No I2DAT action
No I2DAT action or
No I2DAT action
No I2DAT action or
No I2DAT action or
No I2DAT action
Read data byte or
Read data byte
Read data byte or
Read data byte or
Read data byte
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
To I2CON
STA STO SI
X
X
X
0
1
0
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
X
X
X
X
X
0
1
X
X
X
0
1
X
X
X
Next action taken by I
SLA+R will be transmitted; ACK bit will be
received.
As above.
SLA+W will be transmitted; the I
will be switched to MST/TRX mode.
I
enter a slave mode.
A START condition will be transmitted
when the bus becomes free.
Data byte will be received; NOT ACK bit
will be returned.
Data byte will be received; ACK bit will be
returned.
Repeated START condition will be
transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be received; NOT ACK bit
will be returned.
Data byte will be received; ACK bit will be
returned.
Repeated START condition will be
transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
2
C-bus will be released; the I
Chapter 19: LPC17xx I2C0/1/2
UM10360
© NXP B.V. 2010. All rights reserved.
2
C hardware
2
C block will
2
C block
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