LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 521

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 452: PWM Latch Enable Register (PWM1LER - address 0x4001 8050) bit description
UM10360
User manual
Bit
4
5
6
31:7 -
Symbol
Enable PWM
Match 4 Latch
Enable PWM
Match 5 Latch
Enable PWM
Match 6 Latch
Description
Writing a one to this bit allows the last value written to the PWM Match 4 register to be
become effective when the timer is next reset by a PWM Match event. See
“PWM Match Control Register (PWM1MCR - 0x4001
Writing a one to this bit allows the last value written to the PWM Match 5 register to be
become effective when the timer is next reset by a PWM Match event. See
“PWM Match Control Register (PWM1MCR - 0x4001
Writing a one to this bit allows the last value written to the PWM Match 6 register to be
become effective when the timer is next reset by a PWM Match event. See
“PWM Match Control Register (PWM1MCR - 0x4001
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 24: LPC17xx Pulse Width Modulator (PWM)
8014)”.
8014)”.
8014)”.
Section 24.6.4
Section 24.6.4
Section 24.6.4
UM10360
© NXP B.V. 2010. All rights reserved.
521 of 840
Reset
Value
0
0
0
NA