LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 140
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
Available stocks
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Manufacturer
Quantity
Price
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Manufacturer:
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Quantity:
375
Company:
Part Number:
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Manufacturer:
NXP Semiconductors
Quantity:
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LPC1759FBD80,551
Manufacturer:
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NXP Semiconductors
9.6 GPIO usage notes
UM10360
User manual
9.6.1 Example: An instantaneous output of 0s and 1s on a GPIO port
9.6.2 Writing to FIOSET/FIOCLR vs. FIOPIN
Solution 1: using 32-bit (word) accessible fast GPIO registers
FIO0MASK = 0xFFFF00FF ;
FIO0PIN = 0x0000A500;
Solution 2: using 16-bit (half-word) accessible fast GPIO registers
FIO0MASKL = 0x00FF;
FIO0PINL = 0xA500;
Solution 3: using 8-bit (byte) accessible fast GPIO registers
FIO0PIN1 = 0xA5;
Writing to the FIOSET/FIOCLR registers allow a program to easily change a port’s output
pin(s) to both high and low levels at the same time. When FIOSET or FIOCLR are used,
only pin/bit(s) written with 1 will be changed, while those written as 0 will remain
unaffected.
Writing to the FIOPIN register enables instantaneous output of a desired value on the
parallel GPIO. Data written to the FIOPIN register will affect all pins configured as outputs
on that port: zeroes in the value will produce low level pin outputs and ones in the value
will produce high level pin outputs.
A subset of a port’s pins may be changed by using the FIOMASK register to define which
pins are affected. FIOMASK is set up to contain zeroes in bits corresponding to pins that
will be changed, and ones for all others. Solution 2 from
output of 0xA5 on PORT0 pins 15 to 8 while preserving all other PORT0 output pins as
they were before.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 9: LPC17xx General Purpose Input/Output (GPIO)
Section 9.6.1
UM10360
above illustrates
© NXP B.V. 2010. All rights reserved.
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