LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 756

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.3.5.1.1 Wait for interrupt
34.3.5.1.2 Wait for event
34.3.5.1 Entering sleep mode
34.3.5 Power management
Note: NXP devices based on the Cortex-M3 processor, including the LPC17xx,
support additional reduced power modes. See
information on all available reduced power modes.
The Cortex-M3 processor sleep modes reduce power consumption:
The SLEEPDEEP bit of the SCR selects which sleep mode is used, see
“System Control
see
This section describes the mechanisms for entering sleep mode, and the conditions for
waking up from sleep mode.
This section describes the mechanisms software can use to put the processor into sleep
mode.
The system can generate spurious wakeup events, for example a debug operation wakes
up the processor. Therefore software must be able to put the processor back into sleep
mode after such an event. A program might have an idle loop to put the processor back to
sleep mode.
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the
processor executes a WFI instruction it stops executing instructions and enters sleep
mode. See
Note: LPC17xx devices based on the Cortex-M3 processor do not implement
external events.
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of
an one-bit event register. When the processor executes a WFE instruction, it checks this
register:
See
If the event register is 1, this indicate that the processor must not enter sleep mode on
execution of a WFE instruction. Typically, this is because an external event signal is
asserted, or a processor in the system has executed an SEV instruction, see
Section 34.2.10.9
•
•
•
•
Sleep mode stops the processor clock
Deep sleep mode stops the system clock and switches off the PLL and flash memory.
if the register is 0 the processor stops executing instructions and enters sleep mode
if the register is 1 the processor clears the register to 0 and continues executing
instructions without entering sleep mode.
Section 4.8 “Power
Section 34.2.10.11 “WFE”
Section 34.2.10.12 “WFI”
All information provided in this document is subject to legal disclaimers.
Register”. For more information about the behavior of the sleep modes
“SEV”. Software cannot access this register directly.
Rev. 2 — 19 August 2010
control”.
for more information.
for more information.
Chapter 34: Appendix: Cortex-M3 user guide
Section 4.8 “Power control”
UM10360
© NXP B.V. 2010. All rights reserved.
Section 34.4.3.7
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