LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 380

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 348. LUT Error Address register (LUTerrAd - address 0x4003 C018) bit description
Table 349. LUT Error register (LUTerr - address 0x4003 C01C) bit description
Table 350. Global FullCAN Enable register (FCANIE - address 0x4003 C020) bit description
Table 351. FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0x4003 C024) bit description
UM10360
User manual
Bit
1:0
10:2
31:11 -
Bit
0
31:1
Bit
0
31:1
Bit
0
...
31
Symbol
-
LUTerrAd
Symbol
LUTerr
-
Symbol
FCANIE
-
Symbol
IntPnd0
IntPndx (0<x<31)
IntPnd31
16.14.10 LUT Error register (LUTerr - 0x4003 C01C)
16.14.12 FullCAN Interrupt and Capture registers (FCANIC0 - 0x4003 C024 and
16.14.11 Global FullCANInterrupt Enable register (FCANIE - 0x4003 C020)
16.14.9 LUT Error Address register (LUTerrAd - 0x4003 C018)
Description
This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of
the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This
condition is ORed with the “other CAN” interrupts from the CAN controllers, to produce the
request that is connected to the NVIC.
Reserved, the value read from a reserved bit is not defined.
Description
Global FullCAN Interrupt Enable. When 1, this interrupt is enabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup
Table RAM, at which the Acceptance Filter encountered an error in the content of the
tables.
Reserved, the value read from a reserved bit is not defined.
information under which address during an ID screening an error in the look-up table was
encountered. Any read of the LUTerrorAddr Filter block can be used for a look-up table
interrupt.
A write access to the Global FullCAN Interrupt Enable register is only possible when the
Acceptance Filter is in the off mode.
FCANIC1 - 0x4003 C028)
For detailed description on these two registers, see
Description
FullCan Interrupt Pending bit 0.
FullCan Interrupt Pending bit x.
FullCan Interrupt Pending bit 31.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 16.16.2 “FullCAN
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
NA
0
NA
Reset Value
0
NA
Reset Value
0
NA
Reset Value
0
0
0
interrupts”.
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