LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 16

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
For these areas, both attempted data access and instruction fetch generate an exception.
In addition, a Bus Fault exception is generated for any instruction fetch that maps to an
AHB or APB peripheral address.
Within the address space of an existing APB peripheral, an exception is not generated in
response to an access to an undefined address. Address decoding within each peripheral
is limited to that needed to distinguish defined registers within the peripheral itself. For
example, an access to address 0x4000 D000 (an undefined address within the UART0
space) may result in an access to the register defined at address 0x4000 C000. Details of
such address aliasing within a peripheral space are not defined in the LPC17xx
documentation and are not a supported feature.
If software executes a write directly to the flash memory, the flash accelerator will
generate a Bus Fault exception. Flash programming must be accomplished by using the
specified flash programming interface provided by the Boot Code.
Note that the Cortex-M3 core stores the exception flag along with the associated
instruction in the pipeline and processes the exception only if an attempt is made to
execute the instruction fetched from the disallowed address. This prevents accidental
aborts that could be caused by prefetches that occur when code is executed very near a
memory boundary.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 2: LPC17xx Memory map
UM10360
© NXP B.V. 2010. All rights reserved.
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