LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 76

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
6.5 Register description
Table 51.
UM10360
User manual
Name
ISER0 to
ISER1
ICER0 to
ICER1
ISPR0 to
ISPR1
ICPR0 to
ICPR1
IABR0 to
IABR1
IPR0 to
IPR8
STIR
Description
Interrupt Set-Enable Registers. These 2 registers allow enabling
interrupts and reading back the interrupt enables for specific
peripheral functions.
Interrupt Clear-Enable Registers. These 2 registers allow disabling
interrupts and reading back the interrupt enables for specific
peripheral functions.
Interrupt Set-Pending Registers. These 2 registers allow changing
the interrupt state to pending and reading back the interrupt
pending state for specific peripheral functions.
Interrupt Clear-Pending Registers. These 2 registers allow
changing the interrupt state to not pending and reading back the
interrupt pending state for specific peripheral functions.
Interrupt Active Bit Registers. These 2 registers allow reading the
current interrupt active state for specific peripheral functions.
Interrupt Priority Registers. These 9 registers allow assigning a
priority to each interrupt. Each register contains the 5-bit priority
fields for 4 interrupts.
Software Trigger Interrupt Register. This register allows software to
generate an interrupt.
NVIC register map
The following table summarizes the registers in the NVIC as implemented in the LPC17xx.
The Cortex-M3 User Guide
All information provided in this document is subject to legal disclaimers.
Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC)
Rev. 2 — 19 August 2010
Section 34.4.2
provides a functional description of the NVIC.
Access Reset
RW
RW
RW
RW
RO
RW
WO
value
0
0
0
0
0
0
0
Address
ISER0 - 0xE000 E100
ISER1 - 0xE000 E104
ICER0 - 0xE000 E180
ICER1 - 0xE000 E184
ISPR0 - 0xE000 E200
ISPR1 - 0xE000 E204
ICPR0 - 0xE000 E280
ICPR1 - 0xE000 E284
IABR0 - 0xE000 E300
IABR1 - 0xE000 E304
IPR0 - 0xE000 E400
IPR1 - 0xE000 E404
IPR2 - 0xE000 E408
IPR3 - 0xE000 E40C
IPR4 - 0xE000 E410
IPR5 - 0xE000 E414
IPR6 - 0xE000 E418
IPR7 - 0xE000 E41C
IPR8 - 0xE000 E420
STIR - 0xE000 EF00
UM10360
© NXP B.V. 2010. All rights reserved.
76 of 840