LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 50

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
4.6.4.1 PLL1 modes
4.6.5 PLL1 Interrupt: PLOCK1
Table 32.
The combinations of PLLE1 and PLLC1 are shown in
Table 33.
The PLOCK1 bit in the PLL1STAT register reflects the lock status of PLL1. When PLL1 is
enabled, or parameters are changed, the PLL requires some time to establish lock under
the new conditions. PLOCK1 can be monitored to determine when the PLL may be
connected for use.
PLOCK1 is connected to the interrupt controller. This allows for software to turn on the
PLL and continue with other functions without having to wait for the PLL to achieve lock.
When the interrupt occurs, the PLL may be connected, and the interrupt disabled.
PLOCK1 appears as interrupt 48 in
whenever PLL1 is locked, so if the interrupt is used, the interrupt service routine must
disable the PLOCK1 interrupt prior to exiting.
Bit
4:0
6:5
7
8
9
10
31:11 -
PLLC1
0
0
1
1
Symbol
MSEL1
PSEL1
-
PLLE1_STAT Read-back for the PLL1 Enable bit. When one, PLL1 is currently
PLLC1_STAT Read-back for the PLL1 Connect bit. When PLLC and PLLE are
PLOCK1
PLLE1
0
1
0
1
PLL1 Status register (PLL1STAT - address 0x400F C0A8) bit description
PLL1 control bit combinations
All information provided in this document is subject to legal disclaimers.
PLL1 Function
PLL1 is turned off and disconnected.
PLL1 is active, but not yet connected. PLL1 can be connected after PLOCK1
is asserted.
Same as 00 combination. This prevents the possibility of PLL1 being
connected without also being enabled.
PLL1 is active and has been connected. The clock for the USB subsystem is
sourced from PLL1.
Description
Read-back for the PLL1 Multiplier value. This is the value currently
used by PLL1.
Read-back for the PLL1 Divider value. This is the value currently
used by PLL1.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
activated. When zero, PLL1 is turned off. This bit is automatically
cleared when Power-down mode is activated.
both one, PLL1 is connected as the clock source for the
microcontroller. When either PLLC or PLLE is zero, PLL1 is
bypassed and the oscillator clock is used directly by the
microcontroller. This bit is automatically cleared when Power-down
mode is activated.
Reflects the PLL1 Lock status. When zero, PLL1 is not locked.
When one, PLL1 is locked onto the requested frequency.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 2 — 19 August 2010
Table
Chapter 4: LPC17xx Clocking and power control
50. Note that PLOCK1 remains asserted
Table
33.
UM10360
© NXP B.V. 2010. All rights reserved.
50 of 840
Reset
value
0
0
NA
0
0
0
NA