LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 245
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
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Manufacturer:
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Table 241. SIE command code table
Table 242. Set Address command bit description
UM10360
User manual
Command name
Device commands
Set Address
Configure Device
Set Mode
Read Current Frame Number
Read Test Register
Set Device Status
Get Device Status
Get Error Code
Read Error Status
Endpoint Commands
Select Endpoint
Select Endpoint/Clear Interrupt
Set Endpoint Status
Clear Buffer
Validate Buffer
Bit
6:0
7
Symbol
DEV_ADDR
DEV_EN
11.12.1 Set Address (Command: 0xD0, Data: write 1 byte)
11.12.2 Configure Device (Command: 0xD8, Data: write 1 byte)
Description
Device address set by the software. After a bus reset this field is set to 0x00.
Device Enable. After a bus reset this bit is set to 1.
0: Device will not respond to any packets.
1: Device will respond to packets for function address DEV_ADDR.
The Set Address command is used to set the USB assigned address and enable the
(embedded) function. The address set in the device will take effect after the status stage
of the control transaction. After a bus reset, DEV_ADDR is set to 0x00, and DEV_EN is
set to 1. The device will respond to packets for function address 0x00, endpoint 0 (default
endpoint).
A value of 1 written to the register indicates that the device is configured and all the
enabled non-control endpoints will respond. Control endpoints are always enabled and
respond even if the device is not configured, in the default state.
Recipient
Device
Device
Device
Device
Device
Device
Device
Device
Device
Endpoint 0
Endpoint 1
Endpoint xx
Endpoint 0
Endpoint 1
Endpoint xx
Endpoint 0
Endpoint 1
Endpoint xx
Selected Endpoint
Selected Endpoint
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Code (Hex)
41
D0
D8
F3
F5
FD
FE
FE
FF
FB
00
01
xx
40
40
41
F2
FA
xx + 40
xx + 40
Chapter 11: LPC17xx USB device controller
Data phase
Write 1 byte
Write 1 byte
Write 1 byte
Read 1 or 2 bytes
Read 2 bytes
Write 1 byte
Read 1 byte
Read 1 byte
Read 1 byte
Read 1 byte (optional)
Read 1 byte (optional)
Read 1 byte (optional)
Read 1 byte
Read 1 byte
Read 1 byte
Write 1 byte
Write 1 byte
Write 1 byte
Read 1 byte (optional)
None
UM10360
© NXP B.V. 2010. All rights reserved.
Reset value
0x00
0
245 of 840
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