LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 363

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 323. CAN Error Warning Limit register (CAN1EWL - address 0x4004 4018, CAN2EWL - address 0x4004 8018)
Table 324. CAN Status Register (CAN1SR - address 0x4004 401C, CAN2SR - address 0x4004 801C) bit description
UM10360
User manual
Bit
7:0
31:8
Bit
0
1
2
3
4
5
6
7
8
9
Symbol Function
EWL
-
Symbol Value
RBS
DOS
TBS1
TCS1
RS
TS1
ES
BS
RBS
DOS
bit description
[1]
[2]
16.7.8 CAN Status Register (CAN1SR - 0x4004 401C, CAN2SR -
During CAN operation, this value is compared to both the Tx and Rx Error Counters. If
either of these counter matches this value, the Error Status (ES) bit in CANSR is set.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
0(locked)
1(released)
0(incomplete) The previously requested transmission for Tx Buffer 1 is not complete.
1(complete)
0(idle)
1(transmit)
Note that a content change of the Error Warning Limit Register is possible only if the
Reset Mode was entered previously. An Error Status change (Status Register) and an
Error Warning Interrupt forced by the new register content will not occur until the Reset
Mode is cancelled again.
0x4004 801C)
This read-only register contains three status bytes in which the bits not related to
transmission are identical to the corresponding bits in the Global Status Register, while
those relating to transmission reflect the status of each of the 3 Tx Buffers.
Function
Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.
Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.
Transmit Buffer Status 1.
Software cannot access the Tx Buffer 1 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a
message is either waiting for transmission or is in transmitting process.
Software may write a message into the Transmit Buffer 1 and its CANxTFI,
CANxTID, CANxTDA, and CANxTDB registers.
Transmission Complete Status.
The previously requested transmission for Tx Buffer 1 has been successfully
completed.
Receive Status. This bit is identical to the RS bit in the GSR.
Transmit Status 1.
There is no transmission from Tx Buffer 1.
The CAN Controller is transmitting a message from Tx Buffer 1.
Error Status. This bit is identical to the ES bit in the CANxGSR.
Bus Status. This bit is identical to the BS bit in the CANxGSR.
Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.
Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
Reset
Value
96
NA
10
= 0x60 X
Reset
Value
0
0
1
1
1
1
0
0
0
0
363 of 840
RM
Set
0
0
1
x
0
0
0
0
0
0
RM
Set