LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 353

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
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[4]
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Table 318. CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit
UM10360
User manual
Bit
0
1
2
3
4
[1][2]
[1][3]
[4]
[5]
[1][6]
A write access to the bits MOD.1 and MOD.2 is possible only if the Reset Mode is entered previously.
Transmit Priority Mode is explained in more detail in
The CAN Controller will enter Sleep Mode, if the Sleep Mode bit is set '1' (sleep), there is no bus activity, and none of the CAN interrupts
is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. The CAN
Controller will wake up if SM is set LOW (wake-up) or there is bus activity. On wake-up, a Wake-up Interrupt is generated. A sleeping
CAN Controller which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits
(Bus-Free sequence). Note that setting of SM is not possible in Reset Mode. After clearing of Reset Mode, setting of SM is possible only
when Bus-Free is detected again.
The LOM and STM bits can only be written if the RM bit is 1 prior to the write operation.
Symbol Value
TR
AT
RRB
CDO
SRR
description
16.7.2 CAN Command Register (CAN1CMR - 0x4004 x004, CAN2CMR -
0 (absent)
1 (present)
0 (no action)
1 (present)
0 (no action)
1 (released)
0 (no action)
1 (clear)
0 (absent)
1 (present)
0x4004 8004)
Writing to this write-only register initiates an action within the transfer layer of the CAN
Controller. Reading this register yields zeroes.
At least one internal clock cycle is needed for processing between two commands.
No transmission request.
Do not abort the transmission.
if not already in progress, a pending Transmission Request for the
The message, previously written to the CANxTFS, CANxTID, and
Function
Transmission Request.
The message, previously written to the CANxTFI, CANxTID, and
optionally the CANxTDA and CANxTDB registers, is queued for
transmission from the selected Transmit Buffer. If at two or all three of
STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit
Buffer will be selected based on the chosen priority scheme (for details
see
Abort Transmission.
selected Transmit Buffer is cancelled.
Release Receive Buffer.
Do not release the receive buffer.
The information in the Receive Buffer (consisting of CANxRFS,
CANxRID, and if applicable the CANxRDA and CANxRDB registers) is
released, and becomes eligible for replacement by the next received
frame. If the next received frame is not available, writing this command
clears the RBS bit in the Status Register(s).
Clear Data Overrun.
Do not clear the data overrun bit.
The Data Overrun bit in Status Register(s) is cleared.
Self Reception Request.
No self reception request.
optionally the CANxTDA and CANxTDB registers, is queued for
transmission from the selected Transmit Buffer and received
simultaneously. This differs from the TR bit above in that the receiver is
not disabled during the transmission, so that it receives the message if its
Identifier is recognized by the Acceptance Filter.
Section 16.5.3 “Transmit Buffers
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 16.5.3 “Transmit Buffers
(TXB)”)
(TXB)”.
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
Reset
Value
0
0
0
0
0
353 of 840
RM
Set
0
0
0
0
0