LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 454

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
19.9.3 Slave Receiver mode
In the slave receiver mode, a number of data bytes are received from a master transmitter
(see
and the I2MASK registers must be configured.
The values on the four I2ADR registers combined with the values on the four I2MASK
registers determines which address(es) the I
are enabled. See sections 19.7.2, 19.7.3, 19.8.7, and
Table 397. I2CONSET used to initialize Slave Receiver mode
The I
to logic 1 to enable the I
acknowledge its own slave address or the General Call address. STA, STO, and SI must
be reset.
When the I2ADR, I2MASK, and I2CON registers have been initialized, the I
until it is addressed by its own slave address followed by the data direction bit which must
be “0” (W) for the I
address and the W bit have been received, the serial interrupt flag (SI) is set and a valid
status code can be read from I2STAT. This status code is used to vector to a state service
routine. The appropriate action to be taken for each of these status codes is detailed in
Table
block is in the master mode (see status 0x68 and 0x78).
If the AA bit is reset during a transfer, the I
to SDA after the next received data byte. While AA is reset, the I
respond to its own slave address or a General Call address. However, the I
monitored and address recognition may be resumed at any time by setting AA. This
means that the AA bit may be used to temporarily isolate the I
Bit
Symbol
Value
Figure
2
C-bus rate settings do not affect the I
400. The slave receiver mode may also be entered if arbitration is lost while the I
7
-
-
95). To initiate the slave receiver mode, I2CON register, the I2ADR registers,
All information provided in this document is subject to legal disclaimers.
2
C block to operate in the slave receiver mode. After its own slave
6
I2EN
1
Rev. 2 — 19 August 2010
2
C block. The AA bit must be set to enable the I
5
STA
0
4
STO
0
2
C block will return a not acknowledge (logic 1)
2
2
C block in the slave mode. I2EN must be set
C block will respond to when slave functions
3
SI
0
19.8.8
Chapter 19: LPC17xx I2C0/1/2
2
AA
1
for details.
2
C block from the I
2
C block does not
UM10360
1
-
-
© NXP B.V. 2010. All rights reserved.
2
C block to
2
2
C block waits
C-bus is still
0
-
-
2
454 of 840
C-bus.
2
C