LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 788

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.4.5.2 MPU Control Register
Table 681. TYPE register bit assignments
The MPU CTRL register:
See the register summary in
are shown in
Table 682. MPU CTRL register bit assignments
When ENABLE and PRIVDEFENA are both set to 1:
Bits
[15:8]
[7:0]
[0]
Bits
[31:3]
[2]
[1]
[0]
•
•
•
enables the MPU
enables the default memory map background region
enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and
FAULTMASK escalated handlers.
Name
-
PRIVDEFENA
HFNMIENA
ENABLE
Table
All information provided in this document is subject to legal disclaimers.
Name
DREGION
-
SEPARATE
682.
Rev. 2 — 19 August 2010
Function
Reserved.
Enables privileged software access to the default memory map:
0 = If the MPU is enabled, disables use of the default memory map.
Any memory access to a location not covered by any enabled
region causes a fault.
1 = If the MPU is enabled, enables use of the default memory map
as a background region for privileged software accesses.
When enabled, the background region acts as if it is region number
-1. Any region that is defined and enabled has priority over this
default map.
If the MPU is disabled, the processor ignores this bit.
Enables the operation of MPU during hard fault, NMI, and
FAULTMASK handlers.
When the MPU is enabled:
0 = MPU is disabled during hard fault, NMI, and FAULTMASK
handlers, regardless of the value of the ENABLE bit
1 = the MPU is enabled during hard fault, NMI, and FAULTMASK
handlers.
When the MPU is disabled, if this bit is set to 1 the behavior is
Unpredictable.
Enables the MPU:
0 = MPU disabled
1 = MPU enabled.
Table 680
Function
Indicates the number of supported MPU data regions:
0x08 = Eight MPU regions.
Reserved.
Indicates support for unified or separate instruction and
date memory maps:
0 = unified.
for the MPU CTRL attributes. The bit assignments
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
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