LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 343

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

16.1 Basic configuration
16.2 CAN controllers
16.3 Features
UM10360
User manual
16.3.1 General CAN features
The CAN1/2 peripherals are configured using the following registers:
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The CAN Controller is designed to provide a full
implementation of the CAN-Protocol according to the CAN Specification Version 2.0B.
Microcontrollers with this on-chip CAN controller are used to build powerful local networks
by supporting distributed real-time control with a very high level of security. The
applications are automotive, industrial environments, and high speed networks as well as
low cost multiplex wiring. The result is a strongly reduced wiring harness and enhanced
diagnostic and supervisory capabilities.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router among a number of CAN buses in
various applications.
The CAN module consists of two elements: the controller and the Acceptance Filter. All
registers and the RAM are accessed as 32-bit words.
1. Power: In the PCONP register
2. Peripheral clock: In the PCLKSEL0 register
3. Wake-up: CAN controllers are able to wake up the microcontroller from Power-down
4. Pins: Select CAN1/2 pins through the PINSEL registers and their pin modes through
5. Interrupts: CAN interrupts are enabled using the CAN1/2IER registers
6. CAN controller initialization: see CANMOD register
•
•
•
UM10360
Chapter 16: LPC17xx CAN1/2
Rev. 2 — 19 August 2010
Remark: On reset, the CAN1/2 blocks are disabled (PCAN1/2 = 0).
PCLK_CAN2, and, for the acceptance filter, PCLK_ACF. Note that these must all be
the same value.
Remark: If CAN baud rates above 100 kbit/s (see
select the IRC as the clock source (see
mode, see
the PINMODE registers
Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register.
Compatible with CAN specification 2.0B, ISO 11898-1.
Multi-master architecture with non destructive bit-wise arbitration.
Bus access priority determined by the message identifier (11-bit or 29-bit).
Section
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
4.8.8.
(Section
(Table
8.5).
46), set bits PCAN1/2.
Table
(Table
17).
Table
40), select PCLK_CAN1,
(Section
322) are needed, do not
16.7.1).
© NXP B.V. 2010. All rights reserved.
(Table
User manual
343 of 840
321).