LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 623

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
32.7 ISP commands
UM10360
User manual
32.7.1 Unlock <Unlock code>
The following commands are accepted by the ISP command handler. Detailed status
codes are supported for each command. The command handler sends the return code
INVALID_COMMAND when an undefined command is received. Commands and return
codes are in ASCII format.
CMD_SUCCESS is sent by ISP command handler only when received ISP command has
been completely executed and the new ISP command can be given by the host.
Exceptions from this rule are "Set Baud Rate", "Write to RAM", "Read Memory", and "Go"
commands.
Table 570. ISP command summary
Table 571. ISP Unlock command
ISP Command
Unlock
Set Baud Rate
Echo
Write to RAM
Read Memory
Prepare sector(s) for
write operation
Copy RAM to Flash
Go
Erase sector(s)
Blank check sector(s)
Read Part ID
Read Boot Code version K
Read serial number
Compare
Command
Input
Return Code
Description
Example
U
Unlock code: 23130
CMD_SUCCESS |
INVALID_CODE |
PARAM_ERROR
This command is used to unlock Flash Write, Erase, and Go commands.
"U 23130<CR><LF>" unlocks the Flash Write/Erase & Go commands.
All information provided in this document is subject to legal disclaimers.
Chapter 32: LPC17xx Flash memory interface and programming
Rev. 2 — 19 August 2010
Usage
U <Unlock Code>
B <Baud Rate> <stop bit>
A <setting>
W <start address> <number of bytes>
R <address> <number of bytes>
P <start sector number> <end sector number>
C <flash address> <RAM address> <number of bytes>
G <address> <Mode>
E <start sector number> <end sector number>
I <start sector number> <end sector number>
J
N
M <address1> <address2> <number of bytes>
10
UM10360
© NXP B.V. 2010. All rights reserved.
Described in
Table 571
Table 572
Table 574
Table 575
Table 576
Table 577
Table 578
Table 579
Table 580
Table 581
Table 582
Table 584
Table 585
Table 586
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