LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 817

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
35.5 Contents
Chapter 1: LPC17xx Introductory information
1.1
1.2
1.3
1.4
1.4.1
1.5
1.6
Chapter 2: LPC17xx Memory map
2.1
2.2
2.3
2.4
Chapter 3: LPC17xx System control
3.1
3.2
3.3
3.4
3.4.1
3.5
3.6
3.6.1
Chapter 4: LPC17xx Clocking and power control
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.5
4.5.1
4.5.1.1
4.5.2
UM10360
User manual
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering information . . . . . . . . . . . . . . . . . . . . . 7
Simplified block diagram . . . . . . . . . . . . . . . . . 8
Architectural overview . . . . . . . . . . . . . . . . . . . 9
Memory map and peripheral addressing. . . . 12
Memory maps. . . . . . . . . . . . . . . . . . . . . . . . . . 12
APB peripheral addresses . . . . . . . . . . . . . . . 14
Memory re-mapping. . . . . . . . . . . . . . . . . . . . . 15
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register description . . . . . . . . . . . . . . . . . . . . 18
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Brown-out detection . . . . . . . . . . . . . . . . . . . . 22
External interrupt inputs . . . . . . . . . . . . . . . . . 23
Summary of clocking and power control
functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Register description . . . . . . . . . . . . . . . . . . . . 30
Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Clock source selection multiplexer . . . . . . . . 34
PLL0 (Phase Locked Loop 0) . . . . . . . . . . . . . 35
Part options summary. . . . . . . . . . . . . . . . . . . . 7
Reset Source Identification Register (RSID -
0x400F C180) . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register description . . . . . . . . . . . . . . . . . . . . 24
Internal RC oscillator . . . . . . . . . . . . . . . . . . . 31
Main oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 31
RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 33
Clock Source Select register (CLKSRCSEL -
0x400F C10C) . . . . . . . . . . . . . . . . . . . . . . . . 34
PLL0 operation . . . . . . . . . . . . . . . . . . . . . . . . 35
PLL0 and startup/boot code interaction . . . . . 35
PLL0 register description . . . . . . . . . . . . . . . . 36
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
1.7
1.7.1
1.8
1.9
1.10
2.5
2.6
3.6.2
3.6.3
3.6.4
3.7
3.7.1
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.5.10
4.5.11
4.5.12
ARM Cortex-M3 processor . . . . . . . . . . . . . . . . 9
On-chip flash memory system. . . . . . . . . . . . 10
On-chip Static RAM. . . . . . . . . . . . . . . . . . . . . 10
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AHB arbitration . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus fault exceptions . . . . . . . . . . . . . . . . . . . . 15
Other system controls and status flags . . . . 28
Cortex-M3 Configuration Options . . . . . . . . . . 9
System options: . . . . . . . . . . . . . . . . . . . . . . . . . 9
Debug related options:. . . . . . . . . . . . . . . . . . . 10
Boot ROM re-mapping . . . . . . . . . . . . . . . . . . . 15
External Interrupt flag register (EXTINT -
0x400F C140) . . . . . . . . . . . . . . . . . . . . . . . . 24
External Interrupt Mode register (EXTMODE -
0x400F C148) . . . . . . . . . . . . . . . . . . . . . . . . 25
External Interrupt Polarity register (EXTPOLAR -
0x400F C14C) . . . . . . . . . . . . . . . . . . . . . . . . 26
System Controls and Status register (SCS -
0x400F C1A0) . . . . . . . . . . . . . . . . . . . . . . . . 28
PLL0 Control register (PLL0CON - 0x400F
C080) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PLL0 Configuration register (PLL0CFG -
0x400F C084) . . . . . . . . . . . . . . . . . . . . . . . . 37
PLL0 Status register (PLL0STAT - 0x400F
C088) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PLL0 Interrupt: PLOCK0 . . . . . . . . . . . . . . . . 39
PLL0 Modes. . . . . . . . . . . . . . . . . . . . . . . . . . 40
PLL0 Feed register (PLL0FEED - 0x400F
C08C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
PLL0 and Power-down mode. . . . . . . . . . . . . 40
PLL0 frequency calculation . . . . . . . . . . . . . . 40
Procedure for determining PLL0 settings. . . . 42
Examples of PLL0 settings . . . . . . . . . . . . . . 43
Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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