LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 196

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the
Command register will start a pause frame transmission. The value inserted into the
pause-timer value field of transmitted pause frames is programmed via the
PauseTimer[15:0] bits in the FlowControlCounter register. When the TxFlowControl bit is
de-asserted, another pause frame having a pause-timer value of 0x0000 is automatically
sent to abort flow control and resume transmission.
When flow control be in force for an extended time, a sequence of pause frames must be
transmitted. This is supported with a mirror counter mechanism. To enable mirror
counting, a nonzero value is written to the MirrorCounter[15:0] bits in the
FlowControlCounter register. When the TxFlowControl bit is asserted, a pause frame is
transmitted. After sending the pause frame, an internal mirror counter is initialized to zero.
The internal mirror counter starts incrementing one every 512 bit-slot times. When the
internal mirror counter reaches the MirrorCounter value, another pause frame is
transmitted with pause-timer value equal to the PauseTimer field from the
FlowControlCounter register, the internal mirror counter is reset to zero and restarts
counting. The register MirrorCounter[15:0] is usually set to a smaller value than register
PauseTimer[15:0] to ensure an early expiration of the mirror counter, allowing time to send
a new pause frame before the transmission on the other side can resume. By continuing
to send pause frames before the transmitting side finishes counting the pause timer, the
pause can be extended as long as TxFlowControl is asserted. This continues until
TxFlowControl is de-asserted when a final pause frame having a pause-timer value of
0x0000 is automatically sent to abort flow control and resume transmission. To disable the
mirror counter mechanism, write the value 0 to MirrorCounter field in the
FlowControlCounter register. When using the mirror counter mechanism, account for
time-of-flight delays, frame transmission time, queuing delays, crystal frequency
tolerances, and response time delays by programming the MirrorCounter conservatively,
typically about 80% of the PauseTimer value.
If the software device driver sets the MirrorCounter field of the FlowControlCounter
register to zero, the Ethernet block will only send one pause control frame. After sending
the pause frame an internal pause counter is initialized at zero; the internal pause counter
is incremented by one every 512 bit-slot times. Once the internal pause counter reaches
the value of the PauseTimer register, the TxFlowControl bit in the Command register will
be reset. The software device driver can poll the TxFlowControl bit to detect when the
pause completes.
The value of the internal counter in the flow control module can be read out via the
FlowControlStatus register. If the MirrorCounter is nonzero, the FlowControlStatus register
will return the value of the internal mirror counter; if the MirrorCounter is zero the
FlowControlStatus register will return the value of the internal pause counter value.
The device driver is allowed to dynamically modify the MirrorCounter register value and
switch between zero MirrorCounter and nonzero MirrorCounter modes.
Transmit flow control is enabled via the ‘TX FLOW CONTROL’ bit in the MAC1
configuration register. If the ‘TX FLOW CONTROL’ bit is zero, then the MAC will not
transmit pause control frames, software must not initiate pause frame transmissions, and
the TxFlowControl bit in the Command register should be zero.
Transmit flow control example
Figure 23
illustrates the transmit flow control.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
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