LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 236

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 223. USB DMA Request Status register (USBDMARSt - address 0x5000 C250) bit description
[1]
Table 224. USB DMA Request Clear register (USBDMARClr - address 0x5000 C254) bit description
UM10360
User manual
Bit
0
1
31:2
Bit
0
1
31:2
Bit
Symbol
Bit
Symbol
Bit
Symbol
DMA can not be enabled for this endpoint and the corresponding bit in the USBDMARSt must be 0.
Symbol
EP0
EP1
EPxx
Symbol
EP0
EP1
EPxx
11.10.7.2 USB DMA Request Clear register (USBDMARClr - 0x5000 C254)
11.10.7.3 USB DMA Request Set register (USBDMARSet - 0x5000 C258)
EP23
EP15
EP7
23
15
7
Value
0
0
0
1
Value
0
0
0
1
Writing one to a bit in this register will clear the corresponding bit in the USBDMARSt
register. Writing zero has no effect.
This register is intended for initialization prior to enabling the DMA for an endpoint. When
the DMA is enabled for an endpoint, hardware clears the corresponding bit in
USBDMARSt on completion of a packet transfer. Therefore, software should not clear the
bit using this register while the endpoint is enabled for DMA operation.
USBDMARClr is a write-only register.
The USBDMARClr bit allocation is identical to the USBDMARSt register
Writing one to a bit in this register sets the corresponding bit in the USBDMARSt register.
Writing zero has no effect.
Description
Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0
bit must be 0).
Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit
must be 0).
Clear the endpoint xx (2 ≤ xx ≤ 31) DMA request.
No effect.
Clear the corresponding bit in USBDMARSt.
Description
Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit
must be 0).
Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit
must be 0).
Endpoint xx (2 ≤ xx ≤ 31) DMA request.
DMA not requested by endpoint xx.
DMA requested by endpoint xx.
EP22
EP14
EP6
22
14
6
All information provided in this document is subject to legal disclaimers.
EP21
EP13
EP5
21
13
5
Rev. 2 — 19 August 2010
EP20
EP12
EP4
20
12
4
Chapter 11: LPC17xx USB device controller
EP19
EP11
EP3
19
11
3
EP18
EP10
EP2
18
10
2
EP17
EP9
EP1
17
UM10360
9
1
© NXP B.V. 2010. All rights reserved.
(Table
Reset value
0
0
0
Reset value
0
0
0
222).
EP16
236 of 840
EP8
EP0
16
8
0