LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 651

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.2.3.3.1 Constant
34.2.3.1 Operands
34.2.3.2 Restrictions when using PC or SP
34.2.3.3 Flexible second operand
An instruction operand can be an ARM register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination
register. When there is a destination register in the instruction, it is usually specified before
the operands.
Operands in some instructions are flexible in that they can either be a register or a
constant. See
Many instructions have restrictions on whether you can use the Program Counter (PC)
or Stack Pointer (SP) for the operands or destination register. See instruction
descriptions for more information.
Remark: Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction
must be 1 for correct execution, because this bit indicates the required instruction set, and
the Cortex-M3 processor only supports Thumb instructions.
Many general data processing instructions have a flexible second operand. This is shown
as Operand2 in the descriptions of the syntax of each instruction.
Operand2 can be a:
You specify an Operand2 constant in the form:
#constant
where constant can be:
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Section 34.2.3.1 “Operands”
Section 34.2.3.2 “Restrictions when using PC or SP”
Section 34.2.3.3 “Flexible second operand”
Section 34.2.3.4 “Shift Operations”
Section 34.2.3.5 “Address alignment”
Section 34.2.3.6 “PC-relative expressions”
Section 34.2.3.7 “Conditional execution”
Section 34.2.3.8 “Instruction width
Section 34.2.3.3.1 “Constant”
Section 34.2.3.3.2 “Register with optional shift”
any constant that can be produced by shifting an 8-bit value left by any number of bits
within a 32-bit word
any constant of the form 0x00XY00XY
any constant of the form 0xXY00XY00
any constant of the form 0xXYXYXYXY.
Section
All information provided in this document is subject to legal disclaimers.
34.2.3.3.
Rev. 2 — 19 August 2010
selection”.
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
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