LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 632
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
Available stocks
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Manufacturer
Quantity
Price
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Manufacturer:
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Quantity:
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Company:
Part Number:
LPC1759FBD80,551
Manufacturer:
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Part Number:
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Manufacturer:
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NXP Semiconductors
UM10360
User manual
32.8.1 Prepare sector(s) for write operation
returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned
indirectly via memory. Some of the IAP calls require more than 4 parameters. If the ARM
suggested scheme is used for the parameter passing/returning then it might create
problems due to difference in the C compiler implementation from different vendors. The
suggested parameter passing scheme reduces such risk.
The flash memory is not accessible during a write or erase operation. IAP commands,
which results in a flash write/erase operation, use 32 bytes of space in the top portion of
the on-chip RAM for execution. The user program should not be use this space if IAP flash
programming is permitted in the application.
Table 588. IAP Command Summary
This command makes flash write/erase operation a two step process.
IAP Command
Prepare sector(s) for write operation
Copy RAM to Flash
Erase sector(s)
Blank check sector(s)
Read part ID
Read Boot Code version
Read device serial number
Compare
Reinvoke ISP
Fig 138. IAP parameter passing
ARM REGISTER r0
ARM REGISTER r1
All information provided in this document is subject to legal disclaimers.
Chapter 32: LPC17xx Flash memory interface and programming
Rev. 2 — 19 August 2010
Command Code
50
51
52
53
54
55
58
56
57
10
10
10
10
10
10
10
10
10
COMMAND CODE
PARAMETER 1
PARAMETER 2
PARAMETER n
STATUS CODE
RESULT 1
RESULT 2
RESULT n
Described in
Table 589
Table 590
Table 591
Table 592
Table 593
Table 594
Table 595
Table 596
Table 597
UM10360
command
parameter table
command
result table
© NXP B.V. 2010. All rights reserved.
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