LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 147

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
10.9 Pin description
UM10360
User manual
10.8.2 Example PHY Devices
Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block.
Receive flow control frames are automatically handled by the MAC. Transmit flow control
frames can be initiated by software. In half duplex mode, the flow control module will
generate back pressure by sending out continuous preamble only, interrupted by pauses
to prevent the jabber limit from being exceeded.
The Ethernet block has a standard Reduced Media Independent Interface (RMII) to
connect to an external Ethernet PHY chip. Registers in the PHY chip are accessed via the
AHB interface through the serial management connection of the MIIM bus, typically
operating at 2.5 MHz.
Some examples of compatible PHY devices are shown in
Table 125. Example PHY Devices
Table 126
Interface (RMII) to the external PHY.
Table 126. Ethernet RMII pin descriptions
Table 127
the external PHY.
Table 127. Ethernet MIIM pin descriptions
Manufacturer
Broadcom
ICS
Intel
LSI Logic
Micrel
National
SMSC
Pin Name
ENET_TX_EN
ENET_TXD[1:0]
ENET_RXD[1:0]
ENET_RX_ER
ENET_CRS
ENET_REF_CLK/
ENET_RX_CLK
Pin Name
ENET_MDC
ENET_MDIO
shows the signals used for Media Independent Interface Management (MIIM) of
shows the signals used for connecting the Reduced Media Independent
All information provided in this document is subject to legal disclaimers.
Type
Output
Input/Output
Type
Output
Output
Input
Input
Input
Input
Rev. 2 — 19 August 2010
Transmit data enable
Receive data, 2 bits.
Pin Description
Transmit data, 2 bits
Receive error.
Carrier sense/data valid.
Reference clock
Pin Description
MIIM clock.
MI data input and output
Part Number(s)
BCM5221
ICS1893
LXT971A
L80223, L80225, L80227
KS8721
DP83847, DP83846, DP83843
LAN83C185
Chapter 10: LPC17xx Ethernet
Table
125.
UM10360
© NXP B.V. 2010. All rights reserved.
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