LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 801

IC ARM CORTEX MCU 512K 80-LQFP

LPC1759FBD80,551

Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr

Specifications of LPC1759FBD80,551

Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551

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35.1 Abbreviations
UM10360
User manual
Table 691. Abbreviations
Acronym
ADC
AHB
AMBA
APB
BOD
CAN
DAC
DCC
DMA
DSP
EOP
ETM
GPIO
IrDA
JTAG
MIIM
PHY
PLL
PWM
RMII
SE0
SPI
SSI
SSP
TTL
UART
USB
UM10360
Chapter 35: Supplementary information
Rev. 2 — 19 August 2010
All information provided in this document is subject to legal disclaimers.
Description
Analog-to-Digital Converter
Advanced High-performance Bus
Advanced Microcontroller Bus Architecture
Advanced Peripheral Bus
BrownOut Detection
Controller Area Network
Digital-to-Analog Converter
Debug Communication Channel
Direct Memory Access
Digital Signal Processing
End Of Packet
Embedded Trace Macrocell
General Purpose Input/Output
Infrared Data Association
Joint Test Action Group
Media Independent Interface Management
Physical Layer
Phase-Locked Loop
Pulse Width Modulator
Reduced Media Independent Interface
Single Ended Zero
Serial Peripheral Interface
Serial Synchronous Interface
Synchronous Serial Port
Transistor-Transistor Logic
Universal Asynchronous Receiver/Transmitter
Universal Serial Bus
Rev. 2 — 19 August 2010
© NXP B.V. 2010. All rights reserved.
User manual
801 of 840

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