LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 11

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
1.10 Block diagram
UM10360
User manual
Fig 2.
LPC1768 block diagram, CPU and buses
Vbat
ARM Cortex-M3
AHB Matrix
I-code
Multilayer
bus
ultra-low power
TEST/DEBUG
INTERFACE
regulator
interface
oscillator
JTAG
32 kHz
D-code
bus
APB slave group 0
RTC Power Domain
GPIO interrupt control
Pin connect block
Capture/compare
Watchdog timer
UARTs 0 & 1
timers 0 & 1
12-bit ADC
CAN 1 & 2
I
2
Debug Port
System
PWM1
C 0 & 1
SSP1
Real Time Clock
SPI0
bus
Backup registers
(20 bytes)
All information provided in this document is subject to legal disclaimers.
controller
DMA
Rev. 2 — 19 August 2010
APB bridge
APB bridge
AHB to
AHB to
Ethernet PHY
Ethernet
10/100
interface
MAC
Chapter 1: LPC17xx Introductory information
interface
DMAC
device,
host,
OTG
USB
USB
regs
Note: shaded peripheral blocks
support General Purpose DMA
Quadrature encoder
APB slave group 1
Motor control PWM
Repetitive interrupt
External interrupts
Capture/compare
USB
regs
controls
internal
clocks
power
System control
UARTs 2 & 3
and
timers 2 & 3
Accelerator
SRAM
SRAM
SRAM
32 kB
16 kB
16 kB
Flash
SSP0
timer
DAC
I
I2S
2
C2
Ethernet
clock generation,
system functions
voltage regulator
regs
power control,
and other
512 kB
Flash
GPIO
ROM
8 kB
HS
UM10360
© NXP B.V. 2010. All rights reserved.
OUT
CLK
Vdd
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