LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 375
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
Available stocks
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Quantity
Price
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Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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NXP Semiconductors
16.13 ID look-up table RAM
UM10360
User manual
The Whole ID Look-up Table RAM is only word accessible. A write access is only possible
during the Acceptance Filter Off or Bypass Mode. Read access is allowed in all
Acceptance Filter Modes.
If Standard (11-bit) Identifiers are used in the application, at least one of 3 tables in
Acceptance Filter RAM must not be empty. If the optional “FullCAN mode” is enabled, the
first table contains Standard identifiers for which reception is to be handled in this mode.
The next table contains individual Standard Identifiers and the third contains ranges of
Standard Identifiers, for which messages are to be received via the CAN Controllers. The
tables of FullCAN and individual Standard Identifiers must be arranged in ascending
numerical order, one per halfword, two per word. Since each CAN bus has its own
address map, each entry also contains the number of the CAN Controller (001-010) to
which it applies.
The table of Standard Identifier Ranges contains paired upper and lower (inclusive)
bounds, one pair per word. These must also be arranged in ascending numerical order.
The disable bits in Standard entries provide a means to turn response, to particular CAN
Identifiers or ranges of Identifiers, on and off dynamically. When the Acceptance Filter
function is enabled, only the disable bits in Acceptance Filter RAM can be changed by
software. Response to a range of Standard addresses can be enabled by writing 32 zero
bits to its word in RAM, and turned off by writing 32 one bits (0xFFFF FFFF) to its word in
RAM. Only the disable bits are actually changed. Disabled entries must maintain the
ascending sequence of Identifiers.
If Extended (29-bit) Identifiers are used in the application, at least one of the other two
tables in Acceptance Filter RAM must not be empty, one for individual Extended Identifiers
and one for ranges of Extended Identifiers. The table of individual Extended Identifiers
must be arranged in ascending numerical order.
Fig 58. Entry in FullCAN and individual standard identifier tables
Fig 59. Entry in standard identifier range table
31
15
31
CONTROLLER
CONTROLLER #
#
All information provided in this document is subject to legal disclaimers.
29
29
13
ABLE
DIS
Rev. 2 — 19 August 2010
26
LOWER IDENTIFIER
USED
NOT
BOUND
26
10
16
CONTROLLER
#
IDENTIFIER
Chapter 16: LPC17xx CAN1/2
10
UPPER IDENTIFIER
UM10360
BOUND
© NXP B.V. 2010. All rights reserved.
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