LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 127

IC ARM CORTEX MCU 512K 80-LQFP

LPC1759FBD80,551

Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr

Specifications of LPC1759FBD80,551

Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551

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NXP Semiconductors
UM10360
User manual
9.5.4 GPIO port Pin value register FIOxPIN (FIO0PIN to FIO4PIN- 0x2009
Table 108. Fast GPIO port output Clear byte and half-word accessible register description
C014 to 0x2009 C094)
This register provides the value of port pins that are configured to perform only digital
functions. The register will give the logic value of the pin regardless of whether the pin is
configured for input or output, or as GPIO or an alternate digital function. As an example,
a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output
as selectable functions. Any configuration of that pin will allow its current logic state to be
read from the corresponding FIOxPIN register.
If a pin has an analog function as one of its options, the pin state cannot be read if the
analog configuration is selected. Selecting the pin as an A/D input disconnects the digital
features of the pin. In that case, the pin value read in the FIOxPIN register is not valid.
Writing to the FIOxPIN register stores the value in the port output register, bypassing the
need to use both the FIOxSET and FIOxCLR registers to obtain the entire written value.
This feature should be used carefully in an application since it affects the entire port.
the FIOxMASK register (see
Generic
Register
name
FIOxCLR3 Fast GPIO Port x output
FIOxCLRL Fast GPIO Port x output
FIOxCLRU Fast GPIO Port x output
Access to a port pin via the FIOxPIN register is conditioned by the corresponding bit of
Description
Clear register 3. Bit 0 in
FIOxCLR3 register
corresponds to pin Px.24 …
bit 7 to pin Px.31.
Clear Lower half-word
register. Bit 0 in FIOxCLRL
register corresponds to pin
Px.0 … bit 15 to pin Px.15.
Clear Upper half-word
register. Bit 0 in FIOxCLRU
register corresponds to pin
Px.16 … bit 15 to Px.31.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 9: LPC17xx General Purpose Input/Output (GPIO)
Section
9.5.5).
Register
length (bits)
& access
8 (byte)
WO
16 (half-word)
WO
16 (half-word)
WO
Reset
value
0x00
0x0000 FIO0CLRL - 0x2009 C01C
0x0000 FIO0CLRU - 0x2009 C01E
PORTn Register
Address & Name
FIO0CLR3 - 0x2009 C01F
FIO1CLR3 - 0x2009 C03F
FIO2CLR3 - 0x2009 C05F
FIO3CLR3 - 0x2009 C07F
FIO4CLR3 - 0x2009 C09F
FIO1CLRL - 0x2009 C03C
FIO2CLRL - 0x2009 C05C
FIO3CLRL - 0x2009 C07C
FIO4CLRL - 0x2009 C09C
FIO1CLRU - 0x2009 C03E
FIO2CLRU - 0x2009 C05E
FIO3CLRU - 0x2009 C07E
FIO4CLRU - 0x2009 C09E
UM10360
© NXP B.V. 2010. All rights reserved.
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