S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 822

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 23 Voltage Regulator (S12VREGL3V3V1)
23.3.2.3
The VREGAPICL register allows the configuration of the VREG_3V3 autonomous periodical interrupt
features.
822
0x02F2
APICLK
Reset
APIES
APIEA
APIFE
LVDS
Field
Field
LVIE
LVIF
2
1
0
7
4
3
2
W
R
APICLK
Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
0 Input voltage V
1 Input voltage V
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
Note: On entering the Reduced Power Mode the LVIF is not cleared by the VREG_3V3.
Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if
APIFE = 0; APICLK cannot be changed if APIFE is set by the same write operation.
0 Autonomous periodical interrupt clock used as source.
1 Bus clock used as source.
Autonomous Periodical Interrupt External Select Bit — Selects the waveform at the external pin.If set, at the
external pin a clock is visible with 2 times the selected API Period
be a high pulse at the end of every selected period with the size of half of the min period
level specification for connectivity.
0 At the external periodic high pulses are visible, if APIEA and APIFE is set.
1 At the external pin a clock is visible, if APIEA and APIFE is set.
Autonomous Periodical Interrupt External Access Enable Bit — If set, the waveform selected by bit APIES
can be accessed externally. See device level specification for connectivity.
0 Waveform selected by APIES can not be accessed externally.
1 Waveform selected by APIES can be accessed externally, if APIFE is set.
Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer
when set.
0 Autonomous periodical interrupt is disabled.
1 Autonomous periodical interrupt is enabled and timer starts running.
Autonomous Periodical Interrupt Control Register (VREGAPICL)
0
7
Figure 23-4. Autonomous Periodical Interrupt Control Register (VREGAPICL)
= Unimplemented or Reserved
0
0
6
DDA
DDA
is above level V
is below level V
Table 23-5. VREGAPICL Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Table 23-4. VREGCTRL Field Descriptions
0
0
5
LVIA
LVID
and FPM.
APIES
or RPM or shutdown mode.
0
4
Description
Description
APIEA
0
3
(Table
APIFE
23-9). If not set, at the external pin will
0
2
Freescale Semiconductor
(Table
APIE
0
1
23-9). See device
APIF
0
0