S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 475

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Read: Anytime
Write: Anytime except if PLLSEL = 1
11.3.2.4
This register provides S12XECRG status bits and flags.
Read: Anytime
Write: Refer to each bit for individual write conditions
Freescale Semiconductor
1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by system reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset.
Module Base + 0x0002
Module Base + 0x0003
Reset
Reset
W
W
R
R
f PLL
RTIF
S12XECRG Flags Register (CRGFLG)
0
0
0
7
=
7
If POSTDIV = $00 then f
------------------------------------- -
(
2xPOSTDIV
f VCO
= Unimplemented or Reserved
= Unimplemented or Reserved
Note 1
PORF
Figure 11-5. S12XECRG Post Divider Register (POSTDIV)
0
0
6
6
Figure 11-6. S12XECRG Flags Register (CRGFLG)
)
MC9S12XE-Family Reference Manual Rev. 1.25
Note 2
LVRF
0
0
5
5
PLL
is identical to f
LOCKIF
Note 3
NOTE
0
4
4
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
VCO
LOCK
0
0
3
3
(divide by one).
POSTDIV[4:0]
ILAF
0
0
2
2
SCMIF
0
0
1
1
SCM
0
0
0
0
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