S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 329

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Using this configuration, a byte access of ADDR[n] can cause a comparator match if the databus low byte
by chance contains the same value as ADDR[n+1] because the databus comparator does not feature access
size comparison and uses the mask as a “don’t care” function. Thus masked bits do not prevent a match.
Comparators A and C feature an NDB control bit to determine if a match occurs when the data bus differs
to comparator register contents or when the data bus is equivalent to the comparator register contents.
8.4.2.2
Comparators B and D feature SZ and SZE control bits. If SZE is clear, then the comparator address match
qualification functions the same as for comparators A and C.
If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the
specified type of access causes a match. Thus if configured for a byte access of a particular address, a word
access covering the same address does not lead to match.
8.4.2.3
Comparators A and C each feature an NDB control bit, which allows data bus comparators to be configured
to either trigger on equivalence or trigger on difference. This allows monitoring of a difference in the
contents of an address location from an expected value.
When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by
clearing the corresponding mask bit (DBGxDHM/DBGxDLM), so that it is ignored in the comparison. A
match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register
bits are clear, then a match is based on the address bus only, the data bus is ignored.
When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any
data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored
and prevents a match because no difference can be detected. In this case address bus equivalence does not
cause a match.
Freescale Semiconductor
1. A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address used in the code.
Comparators
Comparators
Comparators
Comparators
Comparator
A and C
B and D
B and D
B and D
Exact Address Comparator Match (Comparators B and D)
Data Bus Comparison NDB Dependency
Table 8-40. Comparator Access Size Considerations
Address
ADDR[n]
ADDR[n]
ADDR[n]
ADDR[n]
MC9S12XE-Family Reference Manual Rev. 1.25
SZE
—
0
1
1
SZ8
NOTE
—
X
0
1
Word and byte accesses of ADDR[n]
Word and byte accesses of ADDR[n]
Word accesses of ADDR[n]
Condition For Valid Match
MOVW #$WORD ADDR[n]
MOVW #$WORD ADDR[n]
MOVW #$WORD ADDR[n]
Byte accesses of ADDR[n]
MOVB #$BYTE ADDR[n]
MOVB #$BYTE ADDR[n]
MOVB #$BYTE ADDR[n]
Chapter 8 S12X Debug (S12XDBGV3) Module
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