S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 583

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of
tap2tap column in
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the
Freescale Semiconductor
SDA
SCL
Table
IBC5-3
(bin)
000
001
010
011
100
101
110
111
15-4. The SCL Tap is used to generated the SCL period and the SDA Tap is used
Table
15-4, all subsequent tap points are separated by 2
MC9S12XE-Family Reference Manual Rev. 1.25
scl2start
Table 15-5. Prescale Divider Encoding
(clocks)
126
14
30
62
2
2
2
6
Table 15-6. Multiplier Factor
IBC7-6
00
01
10
11
scl2stop
(clocks)
SCL Divider
129
17
33
65
7
7
9
9
RESERVED
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
MUL
01
02
04
(clocks)
scl2tap
126
14
30
62
4
4
6
6
SDA Hold
(clocks)
tap2tap
IBC5-3
128
Table
16
32
64
1
2
4
8
as shown in the
15-6.
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