S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 508

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
13.3.2
This section describes in address order all the ADC12B16C registers and their individual bits.
13.3.2.1
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
508
Address
0x002C
Module Base + 0x0000
0x002A
0x002E
0x0024
0x0026
0x0028
WRAP[3-0]
Reset
Field
3-0
W
R
Reserved
ATDDR10
ATDDR11
ATDDR12
ATDDR13
ATDDR14
ATDDR15
Register Descriptions
Name
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-
channel conversions. The coding is summarized in
ATD Control Register 0 (ATDCTL0)
0
7
WRAP3 WRAP2 WRAP1 WRAP0
0
= Unimplemented or Reserved
W
W
W
W
W
W
R
R
R
R
R
R
Figure 13-2. ADC12B16C Register Summary (Sheet 3 of 3)
0
0
6
Bit 7
0
Table 13-3. Multi-Channel Wrap Around Coding
Figure 13-3. ATD Control Register 0 (ATDCTL0)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 13-2. ATDCTL0 Field Descriptions
= Unimplemented or Reserved
0
0
0
5
and
and
and
and
and
and
6
See
See
See
See
See
See
Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
0
5
0
0
4
Multiple Channel Conversions (MULT = 1)
Description
Wraparound to AN0 after Converting
Table
4
WRAP3
13-3.
1
3
Reserved
3
WRAP2
(1)
1
2
2
WRAP1
Freescale Semiconductor
1
1
1
WRAP0
Bit 0
1
0