S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 456
S912XET256J2VAGR
Manufacturer Part Number
S912XET256J2VAGR
Description
16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEQ512J3CAGR.pdf
(1324 pages)
Specifications of S912XET256J2VAGR
Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
256 KB
Data Ram Size
16 KB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, SCI, SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
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Chapter 10 XGATE (S12XGATEV3)
TFR
Operation
TFR RD,CCR: CCR ⇒ RD[3:0]; 0 ⇒ RD[15:4]
TFR CCR,RD: RD[3:0] ⇒ CCR
TFR RD,PC:
Transfers the content of one RISC core register to another.
The TFR RD,PC instruction can be used to implement relative subroutine calls.
Example:
RETADDR ...
SUBR
CCR Effects
Code and CPU Cycles
456
TFR RD,CCR, TFR RD,PC:
N:
Z:
V:
C:
TFR RD,CCR CCR ⇒ RD
TFR CCR,RS RS ⇒ CCR
TFR RD,PCPC+4 ⇒ RD
—
N
Not affected.
Not affected.
Not affected.
Not affected.
—
Z
TFR
BRA
...
JAL
—
V
Source Form
—
C
PC+4 ⇒ RD
R7,PC
SUBR
R7
Transfer from and to Special Registers
;Return address (RETADDR) is stored in R7
;Relative branch to subroutine (SUBR)
;Jump to return address (RETADDR)
MC9S12XE-Family Reference Manual Rev. 1.25
Address
Mode
MON
MON
MON
0
0
0
0
0
0
TFR CCR,RS:
0
0
0
N:
Z:
V:
C:
N
∆
0
0
0
RS[3].
RS[2].
RS[1].
RS[0].
Z
∆
0
0
0
V
∆
Machine Code
RD
RD
RS
C
∆
1
1
1
1
1
1
1
1
1
1
1
1
Freescale Semiconductor
1
1
1
0
0
0
TFR
0
0
1
0
1
0
Cycles
P
P
P
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