S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 131

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

2.3.38
Freescale Semiconductor
Address 0x0251
Field
PTM
PTM
PTM
PTM
Reset
1-0
4
3
2
W
R
Port M general purpose input/output data—Data Register
Port M pin 4 is associated with the RXCAN signal of CAN2 and the routed CAN4 and CAN0, as well as with MOSI
signals of SPI0.
The CAN2 function takes precedence over the routed CAN0, routed CAN4, the routed SPI0 and the general purpose
I/O function if the CAN2 module is enabled. The routed CAN0 function takes precedence over the routed CAN4, the
routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. The routed CAN4 function
takes precedence over the routed SPI0 and general purpose I/O function if the routed CAN4 module is enabled. The
routed SPI0 function takes precedence of the general purpose I/O function if the routed SPI0 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port M general purpose input/output data—Data Register
Port M pin 5 is associated with the TXCAN signal of CAN1 and the routed CAN0, as well as with SS0 signals of SPI0.
The CAN1 function takes precedence over the routed CAN0, the routed SPI0 and the general purpose I/O function
if the CAN1 module is enabled. The routed CAN0 function takes precedence over the routed SPI0 and the general
purpose I/O function if the routed CAN0 module is enabled. The routed SPI0 function takes precedence of the
general purpose I/O function if the routed SPI0 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port M general purpose input/output data—Data Register
Port M pin 4 is associated with the RXCAN signal of CAN1 and the routed CAN0, as well as with MISO signals of
SPI0.
The CAN1 function takes precedence over the routed CAN0, the routed SPI0 and the general purpose I/O function
if the CAN1 module is enabled. The routed CAN0 function takes precedence over the routed SPI0 and the general
purpose I/O function if the routed CAN0 module is enabled. The routed SPI0 function takes precedence of the
general purpose I/O function if the routed SPI0 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port M general purpose input/output data—Data Register
Port M pins 1 and 0 are associated with TXCAN and RXCAN signals of CAN0, respectively.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
PTIM7
Port M Input Register (PTIM)
u
7
= Unimplemented or Reserved
PTIM6
Table 2-33. PTM Register Field Descriptions (continued)
u
6
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 2-36. Port M Input Register (PTIM)
PTIM5
u
5
PTIM4
u
4
Description
u = Unaffected by reset
PTIM3
3
u
Chapter 2 Port Integration Module (S12XEPIMV1)
PTIM2
u
2
PTIM1
u
1
Access: User read
PTIM0
u
0
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