S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 152

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.64
152
Address 0x026B
Write: Anytime.
DDRJ
DDRJ
RDRJ
Field
Field
Reset
7-0
1
0
W
R
Port J data direction—
This register controls the data direction of pin 1.
The enabled SCI2 forces the I/O state to be an output. The DDRM bits revert to controlling the I/O direction of a pin
when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J data direction—
This register controls the data direction of pin 0.
The enabled SCI3 or CS3 signal forces the I/O state to be an output. In those cases the data direction bits will not
change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is
disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port J reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
RDRJ7
Port J Reduced Drive Register (RDRJ)
0
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTH or PTIH registers, when changing the
DDRH register.
RDRJ6
Table 2-59. DDRJ Register Field Descriptions (continued)
0
6
Figure 2-62. Port J Reduced Drive Register (RDRJ)
Table 2-60. RDRJ Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
RDRJ5
0
5
RDRJ4
NOTE
0
4
Description
Description
RDRJ3
3
0
RDRJ2
0
2
Access: User read/write
Freescale Semiconductor
RDRJ1
0
1
RDRJ0
0
0
(1)