S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 673

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

17.4.2
Each time-out event can be used to trigger an interrupt service request. For each timer channel, an
individual bit PINTE in the PIT interrupt enable (PITINTE) register exists to enable this feature. If PINTE
is set, an interrupt service is requested whenever the corresponding time-out flag PTF in the PIT time-out
flag (PITTF) register is set. The flag can be cleared by writing a one to the flag bit.
17.4.3
The PIT module contains eight hardware trigger signal lines PITTRIG[7:0], one for each timer channel.
These signals can be connected on SoC level to peripheral modules enabling e.g. periodic ATD conversion
(please refer to the device overview for the mapping of PITTRIG[7:0] signals to peripheral modules).
Whenever a timer channel time-out is reached, the corresponding PTF flag is set and the corresponding
trigger signal PITTRIG triggers a rising edge. The trigger feature requires a minimum time-out period of
two bus clock cycles because the trigger is asserted high for at least one bus clock cycle. For load register
values PITLD = 0x0001 and PITMTLD = 0x0002 the flag setting, trigger timing and a restart with force
load is shown in
Freescale Semiconductor
Note 1. The PTF flag clearing depends on the software
16-Bit Force Load
PITCNT Register
8-Bit Force Load
Timer Counter
8-Bit Micro
PTF Flag
Bus Clock
PITTRIG
Interrupt Interface
Hardware Trigger
Be careful when resetting the PITE, PINTE or PITCE bits in case of pending
PIT interrupt requests, to avoid spurious interrupt requests.
Figure
1
00
0
17-28.
2
0001
Time-Out Period
Figure 17-28. PIT Trigger and Flag Signal Timing
1
MC9S12XE-Family Reference Manual Rev. 1.25
0
2
0000
1
0
2
NOTE
0001
1
0
2
0000
1
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
2
Time-Out Period
0001
1
After Restart
0
2
0000
1
0
2
0001
1
0
2
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