S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 276

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 6 Interrupt (S12XINTV2)
6.5.3
6.5.3.1
Only I bit maskable interrupt requests which are configured to be handled by the CPU are capable of
waking the MCU from wait mode.
Since bus and core clocks are disabled in stop mode, only interrupt requests that can be generated without
these clocks can wake the MCU from stop mode. These are listed in the device overview interrupt vector
table. Only I bit maskable interrupt requests which are configured to be handled by the CPU are capable
of waking the MCU from stop mode.
To determine whether an I bit maskable interrupt is qualified to wake up the CPU or not, the same settings
as in normal run mode are applied during stop or wait mode:
The X bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the
X bit in CCR is set. If the X bit maskable interrupt request is used to wake-up the MCU with the X bit in
the CCR set, the associated ISR is not called. The CPU then resumes program execution with the
instruction following the WAI or STOP instruction. This features works following the same rules like any
interrupt request, i.e. care must be taken that the X interrupt request used for wake-up remains active at
least until the system begins execution of the instruction following the WAI or STOP instruction;
otherwise, wake-up may not occur.
276
•
•
•
Processing Levels
If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU.
An I bit maskable interrupt is ignored if it is configured to a priority level below or equal to the
current IPL in CCR.
I bit maskable interrupt requests which are configured to be handled by the XGATE module are not
capable of waking up the CPU.
Stacked IPL
IPL in CCR
Wake Up from Stop or Wait Mode
CPU Wake Up from Stop or Wait Mode
7
6
5
4
3
2
1
0
Reset
0
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 6-14. Interrupt Processing Example
L4
0
4
L7
0
4
7
L1 (Pending)
L3 (Pending)
RTI
0
4
RTI
0
3
RTI
Freescale Semiconductor
0
1
RTI
0