S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 119

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

1. Read: See individual bit descriptions below.
1. Read: Always reads 0x00
2.3.17
2.3.18
This register is reserved for factory testing of the PIM module and is not available in normal operation.
Freescale Semiconductor
Address 0x001E
Address 0x001F
Write: See individual bit descriptions below.
IRQEN
Write: Unimplemented
IRQE
Field
Reset
Reset
5-0
7
6
W
W
R
R
IRQ select edge sensitive only—
Special modes: Read or write anytime.
Normal & emulation modes: Read anytime, write once.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1
0 IRQ configured for low level recognition.
External IRQ enable—
Read or write anytime.
1 External IRQ pin is connected to interrupt logic.
0 External IRQ pin is disconnected from interrupt logic.
Reserved—
IRQE
IRQ Control Register (IRQCR)
PIM Reserved Register
and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0
0
0
7
7
Writing to this register when in special modes can alter the pin functionality.
= Unimplemented or Reserved
= Unimplemented or Reserved
IRQEN
1
0
0
6
6
Table 2-17. IRQCR Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 2-15. IRQ Control Register (IRQCR)
Figure 2-16. PIM Reserved Register
0
0
0
0
5
5
NOTE
0
0
0
0
4
4
Description
3
0
0
3
0
0
Chapter 2 Port Integration Module (S12XEPIMV1)
0
0
0
0
2
2
Access: User read/write
0
0
0
0
1
1
Access: User read
0
0
0
0
0
0
119
(1)
(1)